Software is becoming increasingly complex and
there is a growing awareness within software
engineering practice that formal verification
techniques are helpful in dealing with this
growing complexity. As formal verification becomes
increasingly used in the industry as a part of the
design process, there is a constant need for
efficient tool support to deal with real-size
applications. In particular, formal verification
is finding its way into areas such as embedded
systems as used in consumer electronics, time
dependent systems occurring in safety critical
systems, as well as communication and security
protocols.
The workshop aim is to reveal the current
state-of-the-art in the field and the degree in
which the research results are applied in
practice. Theoretical results, algorithms and case
studies are equally welcome.
Topics:
Topics include, but
are not limited to, the following areas:
- formal verification
-
specification and modeling
- automated deduction
- model checking
- compositional methods
- abstraction, symmetry and induction
- embedded systems and software
- computer security
- tools and case studies
- industrial applications
Submission
of Papers
All paper submissions will
be handled electronically and should be
prepared according to SYNASC'04 instructions.
Full papers accepted for presentation will be
available in the form of
a special proceeding of CAVIS (with ISBN) during
the workshop.
Papers should be submitted according SYNASC
deadlines to
synasc04@info.uvt.ro
Program
chairs:
Tudor Jebelean <
tjebelea@risc.uni-linz.ac.at
>
Marius Minea
< marius@cs.utt.ro
>
